Technical Field
This disclosure relates to electronic design automation (EDA). More specifically, this disclosure relates to buffer chain management for alleviating routing congestion.
Related Art
Advances in process technology and an almost unlimited appetite for consumer electronics have fueled a rapid increase in the size and complexity of integrated circuit (IC) designs. The performance of EDA tools is very important because it reduces the time to market for IC designs.
Placement and routing are two important processes that are performed in an EDA flow. Placement involves determining locations for circuit objects (e.g., cells instances, macros, etc.) in the circuit design. Routing involves determining routes for metal wires which electrically connect circuit objects to produce circuits that perform desired functions. Performing placement and routing on large circuit designs using conventional techniques and can take a long time and/or lead to poor quality results. Hence, it is desirable to improve the performance and quality of results of placement and routing, especially for large circuit designs.